The present invention is related to the subject matter of the copending U.S. patent application Ser. No. 450,153, filed Dec. 15, 1982, of Henry John Caulfield, for Systolic Array Processing, which discloses subject matter generic to some of the matter in the present application; and Ser. No. 459,168, filed Jan. 19, 1983 (the same date on which the present application was filed), of H. J. Caulfield, for Polynomial Evaluation, which discloses most of the subject matter in the present application. Said applications are assigned to the assignee of the present invention. Also said earlier application is hereby incorporated hereinto by reference and made a part hereof the same as if fully set forth herein, for purposes of indicating the background of the present invention and illustrating the state of the art.
Except where otherwise indicated herein, the electrooptic components employed in typical embodiments of the present invention are now well known. Convenient ways of making them are described in the above mentioned patent applications and in the references cited therein and herein.
The disclosure in the earlier copending application includes the paper H. J. Caulfield, et al.sup.(2) wherein it is shown how certain algorithms for matrix-vector multiplication can be implemented using acoustooptic cells for multiplication and input data transfer and using CCD detector arrays for accumulation and output of the results. No 2-D matrix mask is required; matrix changes are implemented electronically. A system for multiplying a 50-component nonnegative-real matrix is described. Modifications for bipolar-real and complex-valued processing are possible, as are extensions to matrix-matrix multiplication and multiplication of a vector by multiple matrices.
During the last several years, Kung and Leierson at Carnegie-Mellon University.sup.(1,5) have developed a new type of computational architecture which they call "systolic array processing". Although there are numerous architectures for systolic array processing, a general feature is a flow of data through similar or identical arithmetic or logic units where fixed operations, such as multiplications and additions, are performed. The data tend to flow in a pulsating manner, hence the name "systolic". Systolic array processors appear to offer certain design and speed advantages for VLSI implementation over previous calculational algorithms for such operations as matrix-vector multiplication, matrix-matrix multiplication, pattern recognition in context, and digital filtering. The earlier copending application deals with improving systolic array processors by using optical input and output as well as new architectures for optical signal processing, particularly for multiplications involving at least one matrix; and it points out that many other operations ca be performed in an analogous manner.